1. Field of the Invention
The invention relates to a semiconductor structure, especially to a high voltage laterally double-diffused metal oxide semiconductor (LDMOS) structure.
2. Related Art
In general the high voltage laterally double-diffused metal oxide semiconductor (LDMOS) structure is a semiconductor structure operated in the high voltage range of 20–700V. It can easily be integrated on a single chip and manufactured in CMOS or BiCMOS process, and is used for accelerating the processing of control, logic and power switching.
For the high voltage LDMOS structure, the surface layer of the junction of its drain electrode tends to generate a high intensity electric field, therefore its breakdown voltage frequently is not capable of meeting the actual requirements. In view of this problem, numerous methods have been utilized to avoid the occurrence of the above-mentioned situation, so as to raise the breakdown voltage. For example, please refer to FIG. 1, which shows the cross section of a conventional high voltage MOS structure. As shown in FIG. 1, the conventional MOS structure includes: a P-type substrate 1, a N+ type drain electrode layer 3, a P-type layer 4, a N-type extended drift layer 5, a source electrode 6, a drain electrode 7, insulator layers 8,8′,8″, a gate electrode 9, field plate layers 6′,7′, and the field plate layers 6′,7′ and additional field plate layer 10.
In the above-mentioned structure, the N-type extended drift layer 5 and the field plate layer 6′ are used to avoid the generation of the field concentration on the edge of the gate electrode 9, and field plate layers 7′, 10 are used to reduce the field concentration for the interface between the N+ type drain electrode layer 3 and N-type extended drift layer 5.
In addition, please refer to FIG. 2, which shows one of the several MOS structures as disclosed in U.S. Pat. No. 4,614,959. In this structure, the field plate layers 6′,7′,10′ on different layers are disposed in interleaving arrangement and are utilized to shield the N-type extended drift layer 5, thus to further reduce the electric field concentration.
From the above example, it is evident that one of the urgent problems pending to be solved is how to reduce the field concentration generated by the gate electrode interface or the interface between the N+ type drain electrode layer 3 and the N-type extended drift layer 5, so as to obtain a high voltage LDMOS structure, having a high breakdown voltage and low on resistance.